Linux server.nvwebsoft.co.in 3.10.0-1160.114.2.el7.x86_64 #1 SMP Wed Mar 20 15:54:52 UTC 2024 x86_64
Apache
: 162.240.12.249 | : 52.15.49.90
202 Domain
8.1.31
nbspublicschool
www.github.com/MadExploits
Terminal
AUTO ROOT
Adminer
Backdoor Destroyer
Linux Exploit
Lock Shell
Lock File
Create User
CREATE RDP
PHP Mailer
BACKCONNECT
UNLOCK SHELL
HASH IDENTIFIER
CPANEL RESET
CREATE WP USER
README
+ Create Folder
+ Create File
/
usr /
include /
linux /
[ HOME SHELL ]
Name
Size
Permission
Action
byteorder
[ DIR ]
drwxr-xr-x
caif
[ DIR ]
drwxr-xr-x
can
[ DIR ]
drwxr-xr-x
dvb
[ DIR ]
drwxr-xr-x
hdlc
[ DIR ]
drwxr-xr-x
hsi
[ DIR ]
drwxr-xr-x
iio
[ DIR ]
drwxr-xr-x
isdn
[ DIR ]
drwxr-xr-x
mmc
[ DIR ]
drwxr-xr-x
netfilter
[ DIR ]
drwxr-xr-x
netfilter_arp
[ DIR ]
drwxr-xr-x
netfilter_bridge
[ DIR ]
drwxr-xr-x
netfilter_ipv4
[ DIR ]
drwxr-xr-x
netfilter_ipv6
[ DIR ]
drwxr-xr-x
nfsd
[ DIR ]
drwxr-xr-x
raid
[ DIR ]
drwxr-xr-x
spi
[ DIR ]
drwxr-xr-x
sunrpc
[ DIR ]
drwxr-xr-x
tc_act
[ DIR ]
drwxr-xr-x
tc_ematch
[ DIR ]
drwxr-xr-x
usb
[ DIR ]
drwxr-xr-x
wimax
[ DIR ]
drwxr-xr-x
a.out.h
7.15
KB
-rw-r--r--
acct.h
3.58
KB
-rw-r--r--
adb.h
1.05
KB
-rw-r--r--
adfs_fs.h
873
B
-rw-r--r--
affs_hardblocks.h
1.45
KB
-rw-r--r--
agpgart.h
3.83
KB
-rw-r--r--
aio_abi.h
3.1
KB
-rw-r--r--
apm_bios.h
3.46
KB
-rw-r--r--
arcfb.h
150
B
-rw-r--r--
atalk.h
960
B
-rw-r--r--
atm.h
7.64
KB
-rw-r--r--
atm_eni.h
585
B
-rw-r--r--
atm_he.h
343
B
-rw-r--r--
atm_idt77105.h
892
B
-rw-r--r--
atm_nicstar.h
1.19
KB
-rw-r--r--
atm_tcp.h
1.52
KB
-rw-r--r--
atm_zatm.h
1.57
KB
-rw-r--r--
atmapi.h
889
B
-rw-r--r--
atmarp.h
1.2
KB
-rw-r--r--
atmbr2684.h
3.13
KB
-rw-r--r--
atmclip.h
513
B
-rw-r--r--
atmdev.h
7.44
KB
-rw-r--r--
atmioc.h
1.55
KB
-rw-r--r--
atmlec.h
2.26
KB
-rw-r--r--
atmmpc.h
4.07
KB
-rw-r--r--
atmppp.h
576
B
-rw-r--r--
atmsap.h
4.79
KB
-rw-r--r--
atmsvc.h
1.75
KB
-rw-r--r--
audit.h
18.03
KB
-rw-r--r--
auto_fs.h
2.53
KB
-rw-r--r--
auto_fs4.h
4.3
KB
-rw-r--r--
auxvec.h
1.4
KB
-rw-r--r--
ax25.h
2.7
KB
-rw-r--r--
b1lli.h
1.62
KB
-rw-r--r--
baycom.h
820
B
-rw-r--r--
bfs_fs.h
1.79
KB
-rw-r--r--
binfmts.h
565
B
-rw-r--r--
blkpg.h
1.53
KB
-rw-r--r--
blktrace_api.h
4.38
KB
-rw-r--r--
bpf.h
22.04
KB
-rw-r--r--
bpf_common.h
1.2
KB
-rw-r--r--
bpf_perf_event.h
453
B
-rw-r--r--
bpqether.h
952
B
-rw-r--r--
bsg.h
2.37
KB
-rw-r--r--
bt-bmc.h
508
B
-rw-r--r--
btrfs.h
25.07
KB
-rw-r--r--
can.h
5.46
KB
-rw-r--r--
capability.h
11.25
KB
-rw-r--r--
capi.h
2.99
KB
-rw-r--r--
cciss_defs.h
3.14
KB
-rw-r--r--
cciss_ioctl.h
2.63
KB
-rw-r--r--
cdrom.h
28.12
KB
-rw-r--r--
cgroupstats.h
2.1
KB
-rw-r--r--
chio.h
5.16
KB
-rw-r--r--
cm4000_cs.h
1.68
KB
-rw-r--r--
cn_proc.h
3.19
KB
-rw-r--r--
coda.h
17.09
KB
-rw-r--r--
coda_psdev.h
720
B
-rw-r--r--
coff.h
12.12
KB
-rw-r--r--
connector.h
2.14
KB
-rw-r--r--
const.h
673
B
-rw-r--r--
cramfs_fs.h
2.68
KB
-rw-r--r--
cuda.h
842
B
-rw-r--r--
cyclades.h
16.65
KB
-rw-r--r--
cycx_cfm.h
2.86
KB
-rw-r--r--
dcbnl.h
24.5
KB
-rw-r--r--
dccp.h
6.22
KB
-rw-r--r--
devlink.h
9.66
KB
-rw-r--r--
dlm.h
2.43
KB
-rw-r--r--
dlm_device.h
2.42
KB
-rw-r--r--
dlm_netlink.h
1.04
KB
-rw-r--r--
dlm_plock.h
831
B
-rw-r--r--
dlmconstants.h
4.9
KB
-rw-r--r--
dm-ioctl.h
10.55
KB
-rw-r--r--
dm-log-userspace.h
14.82
KB
-rw-r--r--
dn.h
4.42
KB
-rw-r--r--
dqblk_xfs.h
8.72
KB
-rw-r--r--
edd.h
5.41
KB
-rw-r--r--
efs_fs_sb.h
2.11
KB
-rw-r--r--
elf-em.h
1.83
KB
-rw-r--r--
elf-fdpic.h
1.04
KB
-rw-r--r--
elf.h
12.69
KB
-rw-r--r--
elfcore.h
2.86
KB
-rw-r--r--
errno.h
23
B
-rw-r--r--
errqueue.h
1.1
KB
-rw-r--r--
ethtool.h
71.11
KB
-rw-r--r--
eventpoll.h
1.76
KB
-rw-r--r--
fadvise.h
779
B
-rw-r--r--
falloc.h
2.72
KB
-rw-r--r--
fanotify.h
3.52
KB
-rw-r--r--
fb.h
16
KB
-rw-r--r--
fcntl.h
2.16
KB
-rw-r--r--
fd.h
11.31
KB
-rw-r--r--
fdreg.h
5.23
KB
-rw-r--r--
fib_rules.h
1.58
KB
-rw-r--r--
fiemap.h
2.65
KB
-rw-r--r--
filter.h
1.99
KB
-rw-r--r--
firewire-cdev.h
42.86
KB
-rw-r--r--
firewire-constants.h
3.16
KB
-rw-r--r--
flat.h
2.04
KB
-rw-r--r--
fou.h
617
B
-rw-r--r--
fs.h
8.47
KB
-rw-r--r--
fsl_hypervisor.h
7.05
KB
-rw-r--r--
fuse.h
16.41
KB
-rw-r--r--
futex.h
4.81
KB
-rw-r--r--
gameport.h
834
B
-rw-r--r--
gen_stats.h
1.5
KB
-rw-r--r--
genetlink.h
1.82
KB
-rw-r--r--
gfs2_ondisk.h
12
KB
-rw-r--r--
gigaset_dev.h
1.35
KB
-rw-r--r--
hdlc.h
574
B
-rw-r--r--
hdlcdrv.h
2.78
KB
-rw-r--r--
hdreg.h
22.11
KB
-rw-r--r--
hid.h
1.79
KB
-rw-r--r--
hiddev.h
6.13
KB
-rw-r--r--
hidraw.h
1.41
KB
-rw-r--r--
hpet.h
680
B
-rw-r--r--
hw_breakpoint.h
679
B
-rw-r--r--
hyperv.h
10.22
KB
-rw-r--r--
hysdn_if.h
1.29
KB
-rw-r--r--
i2c-dev.h
2.37
KB
-rw-r--r--
i2c.h
6.66
KB
-rw-r--r--
i2o-dev.h
11.22
KB
-rw-r--r--
i8k.h
1.4
KB
-rw-r--r--
icmp.h
2.82
KB
-rw-r--r--
icmpv6.h
3.82
KB
-rw-r--r--
if.h
9.26
KB
-rw-r--r--
if_addr.h
1.7
KB
-rw-r--r--
if_addrlabel.h
658
B
-rw-r--r--
if_alg.h
816
B
-rw-r--r--
if_arcnet.h
3.63
KB
-rw-r--r--
if_arp.h
6.3
KB
-rw-r--r--
if_bonding.h
4.66
KB
-rw-r--r--
if_bridge.h
6.46
KB
-rw-r--r--
if_cablemodem.h
922
B
-rw-r--r--
if_eql.h
1.26
KB
-rw-r--r--
if_ether.h
7.25
KB
-rw-r--r--
if_fc.h
1.63
KB
-rw-r--r--
if_fddi.h
3.6
KB
-rw-r--r--
if_frad.h
2.89
KB
-rw-r--r--
if_hippi.h
4.07
KB
-rw-r--r--
if_infiniband.h
1.13
KB
-rw-r--r--
if_link.h
19.58
KB
-rw-r--r--
if_ltalk.h
147
B
-rw-r--r--
if_macsec.h
5.42
KB
-rw-r--r--
if_packet.h
7.15
KB
-rw-r--r--
if_phonet.h
361
B
-rw-r--r--
if_plip.h
596
B
-rw-r--r--
if_ppp.h
29
B
-rw-r--r--
if_pppol2tp.h
3.18
KB
-rw-r--r--
if_pppox.h
4.64
KB
-rw-r--r--
if_slip.h
809
B
-rw-r--r--
if_team.h
2.48
KB
-rw-r--r--
if_tun.h
3.71
KB
-rw-r--r--
if_tunnel.h
3.03
KB
-rw-r--r--
if_vlan.h
1.69
KB
-rw-r--r--
if_x25.h
817
B
-rw-r--r--
ife.h
288
B
-rw-r--r--
igmp.h
2.88
KB
-rw-r--r--
in.h
9.36
KB
-rw-r--r--
in6.h
6.97
KB
-rw-r--r--
in_route.h
873
B
-rw-r--r--
inet_diag.h
2.77
KB
-rw-r--r--
inotify.h
2.85
KB
-rw-r--r--
input.h
32.52
KB
-rw-r--r--
ioctl.h
100
B
-rw-r--r--
ip.h
3.47
KB
-rw-r--r--
ip6_tunnel.h
1.67
KB
-rw-r--r--
ip_vs.h
12.77
KB
-rw-r--r--
ipc.h
1.99
KB
-rw-r--r--
ipmi.h
14.63
KB
-rw-r--r--
ipmi_msgdefs.h
3.21
KB
-rw-r--r--
ipsec.h
884
B
-rw-r--r--
ipv6.h
3.66
KB
-rw-r--r--
ipv6_route.h
1.73
KB
-rw-r--r--
ipx.h
1.79
KB
-rw-r--r--
irda.h
7.31
KB
-rw-r--r--
irqnr.h
104
B
-rw-r--r--
isdn.h
5.58
KB
-rw-r--r--
isdn_divertif.h
1.11
KB
-rw-r--r--
isdn_ppp.h
1.82
KB
-rw-r--r--
isdnif.h
2.25
KB
-rw-r--r--
iso_fs.h
6.29
KB
-rw-r--r--
ivtv.h
2.89
KB
-rw-r--r--
ivtvfb.h
1.12
KB
-rw-r--r--
ixjuser.h
24.53
KB
-rw-r--r--
jffs2.h
6.85
KB
-rw-r--r--
joystick.h
3.5
KB
-rw-r--r--
kd.h
6.04
KB
-rw-r--r--
kdev_t.h
320
B
-rw-r--r--
kernel-page-flags.h
788
B
-rw-r--r--
kernel.h
375
B
-rw-r--r--
kernelcapi.h
956
B
-rw-r--r--
kexec.h
1.92
KB
-rw-r--r--
keyboard.h
12.42
KB
-rw-r--r--
keyctl.h
2.98
KB
-rw-r--r--
kvm.h
33.89
KB
-rw-r--r--
kvm_para.h
819
B
-rw-r--r--
l2tp.h
4.98
KB
-rw-r--r--
libc-compat.h
4.03
KB
-rw-r--r--
limits.h
874
B
-rw-r--r--
llc.h
2.98
KB
-rw-r--r--
loop.h
2.31
KB
-rw-r--r--
lp.h
3.72
KB
-rw-r--r--
lwtunnel.h
839
B
-rw-r--r--
magic.h
2.9
KB
-rw-r--r--
major.h
4.48
KB
-rw-r--r--
map_to_7segment.h
7.02
KB
-rw-r--r--
matroxfb.h
1.37
KB
-rw-r--r--
mdio.h
13.74
KB
-rw-r--r--
media.h
3.5
KB
-rw-r--r--
mei.h
4.62
KB
-rw-r--r--
membarrier.h
7.71
KB
-rw-r--r--
memfd.h
186
B
-rw-r--r--
mempolicy.h
2.35
KB
-rw-r--r--
meye.h
2.41
KB
-rw-r--r--
mii.h
7.76
KB
-rw-r--r--
minix_fs.h
2.01
KB
-rw-r--r--
mman.h
230
B
-rw-r--r--
mmtimer.h
2.01
KB
-rw-r--r--
mpls.h
1.33
KB
-rw-r--r--
mqueue.h
2.01
KB
-rw-r--r--
mroute.h
4.06
KB
-rw-r--r--
mroute6.h
4.08
KB
-rw-r--r--
msdos_fs.h
6.28
KB
-rw-r--r--
msg.h
3.21
KB
-rw-r--r--
mtio.h
7.92
KB
-rw-r--r--
n_r3964.h
2.29
KB
-rw-r--r--
nbd.h
2.34
KB
-rw-r--r--
ncp.h
4.94
KB
-rw-r--r--
ncp_fs.h
3.27
KB
-rw-r--r--
ncp_mount.h
2.06
KB
-rw-r--r--
ncp_no.h
651
B
-rw-r--r--
ndctl.h
6.6
KB
-rw-r--r--
neighbour.h
4.17
KB
-rw-r--r--
net.h
1.97
KB
-rw-r--r--
net_dropmon.h
1.07
KB
-rw-r--r--
net_namespace.h
609
B
-rw-r--r--
net_tstamp.h
4.06
KB
-rw-r--r--
netconf.h
423
B
-rw-r--r--
netdevice.h
1.46
KB
-rw-r--r--
netfilter.h
1.6
KB
-rw-r--r--
netfilter_arp.h
380
B
-rw-r--r--
netfilter_bridge.h
768
B
-rw-r--r--
netfilter_decnet.h
1.83
KB
-rw-r--r--
netfilter_ipv4.h
2.02
KB
-rw-r--r--
netfilter_ipv6.h
2.04
KB
-rw-r--r--
netlink.h
6.13
KB
-rw-r--r--
netlink_diag.h
1005
B
-rw-r--r--
netrom.h
744
B
-rw-r--r--
nfc.h
7.72
KB
-rw-r--r--
nfs.h
4.31
KB
-rw-r--r--
nfs2.h
1.37
KB
-rw-r--r--
nfs3.h
2.24
KB
-rw-r--r--
nfs4.h
5.95
KB
-rw-r--r--
nfs4_mount.h
1.83
KB
-rw-r--r--
nfs_fs.h
1.51
KB
-rw-r--r--
nfs_idmap.h
2.19
KB
-rw-r--r--
nfs_mount.h
2.32
KB
-rw-r--r--
nfsacl.h
605
B
-rw-r--r--
nl80211.h
270.89
KB
-rw-r--r--
nubus.h
8.17
KB
-rw-r--r--
nvme_ioctl.h
1.55
KB
-rw-r--r--
nvram.h
469
B
-rw-r--r--
omap3isp.h
20.19
KB
-rw-r--r--
omapfb.h
5.72
KB
-rw-r--r--
oom.h
448
B
-rw-r--r--
openvswitch.h
31.79
KB
-rw-r--r--
packet_diag.h
1.5
KB
-rw-r--r--
param.h
78
B
-rw-r--r--
parport.h
3.56
KB
-rw-r--r--
patchkey.h
829
B
-rw-r--r--
pci.h
1.29
KB
-rw-r--r--
pci_regs.h
50.79
KB
-rw-r--r--
perf_event.h
31.96
KB
-rw-r--r--
personality.h
1.99
KB
-rw-r--r--
pfkeyv2.h
9.91
KB
-rw-r--r--
pg.h
2.23
KB
-rw-r--r--
phantom.h
1.55
KB
-rw-r--r--
phonet.h
4.51
KB
-rw-r--r--
pkt_cls.h
12.49
KB
-rw-r--r--
pkt_sched.h
20.63
KB
-rw-r--r--
pktcdvd.h
2.56
KB
-rw-r--r--
pmu.h
5.13
KB
-rw-r--r--
poll.h
22
B
-rw-r--r--
posix_types.h
1.01
KB
-rw-r--r--
ppdev.h
3.07
KB
-rw-r--r--
ppp-comp.h
2.41
KB
-rw-r--r--
ppp-ioctl.h
5.29
KB
-rw-r--r--
ppp_defs.h
4.93
KB
-rw-r--r--
pps.h
4.06
KB
-rw-r--r--
prctl.h
6.75
KB
-rw-r--r--
psample.h
735
B
-rw-r--r--
ptp_clock.h
5.09
KB
-rw-r--r--
ptrace.h
3.08
KB
-rw-r--r--
qnx4_fs.h
2.21
KB
-rw-r--r--
qnxtypes.h
561
B
-rw-r--r--
quota.h
5.78
KB
-rw-r--r--
radeonfb.h
297
B
-rw-r--r--
random.h
1.2
KB
-rw-r--r--
raw.h
302
B
-rw-r--r--
rds.h
7.9
KB
-rw-r--r--
reboot.h
1.25
KB
-rw-r--r--
reiserfs_fs.h
712
B
-rw-r--r--
reiserfs_xattr.h
470
B
-rw-r--r--
resource.h
2.09
KB
-rw-r--r--
rfkill.h
3.5
KB
-rw-r--r--
romfs_fs.h
1.15
KB
-rw-r--r--
rose.h
2.12
KB
-rw-r--r--
route.h
2.21
KB
-rw-r--r--
rtc.h
3.85
KB
-rw-r--r--
rtnetlink.h
17.02
KB
-rw-r--r--
scc.h
4.43
KB
-rw-r--r--
sched.h
2.26
KB
-rw-r--r--
screen_info.h
2.36
KB
-rw-r--r--
sctp.h
29.53
KB
-rw-r--r--
sdla.h
2.71
KB
-rw-r--r--
seccomp.h
1.83
KB
-rw-r--r--
securebits.h
2.58
KB
-rw-r--r--
selinux_netlink.h
1.11
KB
-rw-r--r--
sem.h
2.54
KB
-rw-r--r--
serial.h
3.04
KB
-rw-r--r--
serial_core.h
5.11
KB
-rw-r--r--
serial_reg.h
15.66
KB
-rw-r--r--
serio.h
1.81
KB
-rw-r--r--
shm.h
2.19
KB
-rw-r--r--
signal.h
171
B
-rw-r--r--
signalfd.h
1.07
KB
-rw-r--r--
snmp.h
12.42
KB
-rw-r--r--
sock_diag.h
431
B
-rw-r--r--
socket.h
738
B
-rw-r--r--
sockios.h
5.83
KB
-rw-r--r--
som.h
5.35
KB
-rw-r--r--
sonet.h
2.17
KB
-rw-r--r--
sonypi.h
5.12
KB
-rw-r--r--
sound.h
1.15
KB
-rw-r--r--
soundcard.h
44.96
KB
-rw-r--r--
stat.h
1
KB
-rw-r--r--
stddef.h
1
B
-rw-r--r--
string.h
175
B
-rw-r--r--
suspend_ioctls.h
1.34
KB
-rw-r--r--
swab.h
6.36
KB
-rw-r--r--
synclink.h
8.71
KB
-rw-r--r--
sysctl.h
25.46
KB
-rw-r--r--
sysinfo.h
986
B
-rw-r--r--
target_core_user.h
3.65
KB
-rw-r--r--
taskstats.h
6.83
KB
-rw-r--r--
tcp.h
5.93
KB
-rw-r--r--
tcp_metrics.h
1.45
KB
-rw-r--r--
telephony.h
8.84
KB
-rw-r--r--
termios.h
443
B
-rw-r--r--
time.h
1.54
KB
-rw-r--r--
times.h
215
B
-rw-r--r--
timex.h
6.17
KB
-rw-r--r--
tiocl.h
1.63
KB
-rw-r--r--
tipc.h
5.44
KB
-rw-r--r--
tipc_config.h
14.1
KB
-rw-r--r--
toshiba.h
1.24
KB
-rw-r--r--
tty.h
1.33
KB
-rw-r--r--
tty_flags.h
3.66
KB
-rw-r--r--
types.h
1.4
KB
-rw-r--r--
udf_fs_i.h
634
B
-rw-r--r--
udp.h
1.28
KB
-rw-r--r--
uhid.h
2.15
KB
-rw-r--r--
uinput.h
5
KB
-rw-r--r--
uio.h
668
B
-rw-r--r--
ultrasound.h
4.39
KB
-rw-r--r--
un.h
239
B
-rw-r--r--
unistd.h
157
B
-rw-r--r--
unix_diag.h
1.1
KB
-rw-r--r--
usbdevice_fs.h
6.78
KB
-rw-r--r--
userfaultfd.h
6.59
KB
-rw-r--r--
utime.h
152
B
-rw-r--r--
utsname.h
606
B
-rw-r--r--
uuid.h
1.5
KB
-rw-r--r--
uvcvideo.h
1.6
KB
-rw-r--r--
v4l2-common.h
2.38
KB
-rw-r--r--
v4l2-controls.h
37.34
KB
-rw-r--r--
v4l2-dv-timings.h
25.75
KB
-rw-r--r--
v4l2-mediabus.h
4.55
KB
-rw-r--r--
v4l2-subdev.h
5.27
KB
-rw-r--r--
version.h
332
B
-rw-r--r--
veth.h
161
B
-rw-r--r--
vfio.h
26.54
KB
-rw-r--r--
vhost.h
7.13
KB
-rw-r--r--
videodev2.h
67.36
KB
-rw-r--r--
virtio_9p.h
1.99
KB
-rw-r--r--
virtio_balloon.h
3.71
KB
-rw-r--r--
virtio_blk.h
5.2
KB
-rw-r--r--
virtio_config.h
3.34
KB
-rw-r--r--
virtio_console.h
2.94
KB
-rw-r--r--
virtio_gpu.h
8.23
KB
-rw-r--r--
virtio_ids.h
2.32
KB
-rw-r--r--
virtio_input.h
2.45
KB
-rw-r--r--
virtio_net.h
9.5
KB
-rw-r--r--
virtio_pci.h
6.63
KB
-rw-r--r--
virtio_ring.h
6.18
KB
-rw-r--r--
virtio_rng.h
265
B
-rw-r--r--
virtio_scsi.h
5.13
KB
-rw-r--r--
virtio_types.h
2.11
KB
-rw-r--r--
virtio_vsock.h
3.01
KB
-rw-r--r--
vm_sockets.h
5.13
KB
-rw-r--r--
vsockmon.h
1.78
KB
-rw-r--r--
vt.h
2.98
KB
-rw-r--r--
vtpm_proxy.h
1.62
KB
-rw-r--r--
wait.h
600
B
-rw-r--r--
wanrouter.h
390
B
-rw-r--r--
watchdog.h
2.22
KB
-rw-r--r--
wimax.h
8.17
KB
-rw-r--r--
wireless.h
41.65
KB
-rw-r--r--
wmi.h
1.84
KB
-rw-r--r--
x25.h
3.42
KB
-rw-r--r--
xattr.h
2.53
KB
-rw-r--r--
xfrm.h
11
KB
-rw-r--r--
Delete
Unzip
Zip
${this.title}
Close
Code Editor : v4l2-dv-timings.h
/* * V4L2 DV timings header. * * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA * 02110-1301 USA */ #ifndef _V4L2_DV_TIMINGS_H #define _V4L2_DV_TIMINGS_H #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) /* Sadly gcc versions older than 4.6 have a bug in how they initialize anonymous unions where they require additional curly brackets. This violates the C1x standard. This workaround adds the curly brackets if needed. */ #define V4L2_INIT_BT_TIMINGS(_width, args...) \ { .bt = { _width , ## args } } #else #define V4L2_INIT_BT_TIMINGS(_width, args...) \ .bt = { _width , ## args } #endif /* CEA-861-E timings (i.e. standard HDTV timings) */ #define V4L2_DV_BT_CEA_640X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X480I59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_720X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X576I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_720X576P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1280X720P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1280X720P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1280X720P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1280X720P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1280X720P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1920X1080P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1920X1080P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1920X1080P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1920X1080I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_1920X1080P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1920X1080I60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_1920X1080P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS) \ } /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ #define V4L2_DV_BT_DMT_640X350P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_720X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* VGA resolutions */ #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 #define V4L2_DV_BT_DMT_640X480P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* SVGA resolutions */ #define V4L2_DV_BT_DMT_800X600P56 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_848X480P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(848, 480, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768I43 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ V4L2_DV_BT_STD_DMT, 0) \ } /* XGA resolutions */ #define V4L2_DV_BT_DMT_1024X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* XGA+ resolution */ #define V4L2_DV_BT_DMT_1152X864P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 /* WXGA resolutions */ #define V4L2_DV_BT_DMT_1280X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X960P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA resolutions */ #define V4L2_DV_BT_DMT_1280X1024P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1360X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1360X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1366X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1366X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA+ resolutions */ #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1400X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WXGA+ resolutions */ #define V4L2_DV_BT_DMT_1440X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1440X900P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1600X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* UXGA resolutions */ #define V4L2_DV_BT_DMT_1600X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P65 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WSXGA+ resolutions */ #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1680X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1792X1344P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1856X1392P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 /* WUXGA resolutions */ #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1440P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* WQXGA resolutions */ #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2560X1600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1366X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #endif
Close